A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas at Dallas.
Abstract:
“With recent advances in hardware technologies such as advanced CPUs and GPUs, and the extensive availability of open source libraries, machine learning is permeating a variety of areas, including electronics design automation (EDA). , consists of multiple stages from logic synthesis to place and route. Traditionally, resource and area estimation from one level of design abstraction to the next uses mathematical, statistical, and analytical approaches. However, as technology nodes decrease and the number of cells in a chip increases, traditional estimation methods no longer correlate with the actual post-route values.Machine learning (ML)-based The methodology paves a powerful path for accurately estimating post-route values. This paper presents a comprehensive survey of existing literature in the field of ML applications in EDA, with emphasis on FPGA design automation tools. How ML is applied at various stages to predict congestion, power, performance, and area (PPA) in both high-level synthesis (HLS)-based and register transfer level (RTL)-based FPGA designs. applications in design space exploration and parameterization of computer-aided design (CAD) tools to optimize timing and area requirements. Reinforcement learning is widely used in both FPGA and ASIC physical design flows. Various ML models such as classical regression and classification ML, convolutional neural networks, reinforcement learning, graph convolutional networks, and their applications in EDA are also discussed. ”
find Click here for the technical paper. Published in October 2023.
P. Goswami and D. Bhatia, “Application of machine learning in FPGA EDA tool development,” IEEE Access, doi: 10.1109/ACCESS.2023.3322358.
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